By Clark Pohl, for ENGR3140 (Computer Architecture) at Olin College of Engineering
We’ve focused on the RISC-V instruction set architecture for the duration of this class. But RISC-V is just one way of translating between high-level code and a specific processor implementation. How did we get here? What are the design decisions that led us to the current state of instruction sets? The goal of this zine is to compare RISC-V to some of today’s most prevalent ISAs (x86 in desktops, laptops, and servers, ARM in mobile devices and low-power embedded devices), and to explain the constraints and goals of each ISA.
The computing landscape of today is significantly different from the environment in which the “RISC vs. CISC wars” initially raged, in the 80s, when RISC was starting to spread from academia to industry. In early computer architectures, disc storage size and main memory access latency were significant bottlenecks to a program’s speed. Having fewer total instructions in a program, leaving more complex decoding to the hardware, was beneficial because it resulted in smaller total program size and fewer main memory accesses. However, one of the ideas behind RISC was that a smaller number of simpler instructions could allow for a smaller and faster CPU, freeing up transistors in the CPU logic. As RISC started showing up in major commercial designs, it was uncertain whether RISC computing would truly take off, or if it was pure hype and wouldn’t make a difference in the long run.
The most obvious concern was whether RISC, with its improvement in CPU speed, would actually allow programs to run faster in the context of a commercial processor. Three factors were at play here: the length of each clock cycle, the average number of clock cycles required for an instruction to completely execute, and the number of instructions executed for a program.
In RISC machines, the average instruction could be executed in a single clock cycle, while CISC instructions could take several clock cycles to execute. In addition, a chip using only simpler instructions could afford a shorter clock cycle time than a chip with more complex instructions requiring microcode. However, the path length of a program compiled to RISC instructions – the number of instructions executed in running each program – would be longer with a smaller set of simpler instructions. This is what causes RISC to earn the nickname “Relegate the Important Stuff to the Compiler”. Whether this was a good or bad thing was yet to be seen with different implementations – would the increased number of instructions required to carry out the same program cause a slowdown so great that the corresponding improvements to cycle time and cycles per instruction didn’t actually matter?
Ultimately, both RISC and CISC machines flourished in commercial chips in the 80s and 90s. Currently, the x86 architecture, considered a CISC ISA, dominates in the market of desktops, servers, and laptops, whereas the ARM architecture, an example of a RISC ISA, is prevalent in mobile devices and low-power embedded devices.
The x86 architecture was based on the Intel 8086 microprocessor, whose predecessors included the less-successful 8008 processor, the first 8-bit microprocessor, designed initially for programmable CRT terminals. Its development has focused on backwards compatibility – for example, one can refer to the original 16-bit registers, the extended 32-bit versions of those registers, or the 64-bit registers, using the prefixes “e” for “extended” or “r” for “register” before the original register names.
The Intel 8088 chip, a later variation of the 8086, was used in the IBM PC, which had a huge influence on the PC market. Even now, the design of most PCs was influenced in part by the IBM PC. The IBM PC’s success contributed to the x86 architecture becoming prevalent in desktops and laptops.
x86 has attracted complaints about its inelegance, as well as attempts to fix it – even from Intel itself. But despite the “cruft” accumulated from years of adding new extensions, x86 also has a long history of optimization behind it, in compilers, microarchitecture, and manufacturing, due to being an established industry standard. This makes it difficult for an entirely new architecture to compete with x86 in the same market of desktops and laptops, as other architectures don’t have the years of optimization that have made up for any inherent inefficiencies introduced by the ISA.
In 1983, Acorn Computers began the Acorn RISC Machine project, inspired by the University of California, Berkeley’s RISC research project. However, Berkeley RISC was not explicitly designed for performance in commercial chips: it was made for illustrating the RISC concept, and work on the design started as part of a VLSI design course by Berkeley students. To adapt an architecture originally made with pedagogy in mind to a commercial chip that could perform well in the PC market, ARM made a few key changes.
To achieve better input/output performance, ARM wanted quicker interrupts. Interrupts require information about the current process to be swapped out for information about another process. To handle this, ARM limited its physical address space to 24 bits, allowing the program counter to only take up 24 bits, giving space for the 8 processor flags such that the entire machine state could be saved in a single 32-bit register in one operation. Later generations removed this requirement.
ARM also added new instructions to take advantage of page mode DRAM, allowing subsequent memory accesses that were physically close together to be faster than otherwise. The “S-cycle” instructions could load or save multiple registers in a single page, which notably improved graphics performance.
ARM processors have low power consumption and low heat generation, which makes them ideal for portable battery-powered devices like mobile phones and embedded systems. This has made ARM incredibly successful due to the prevalence of mobile phones and tablets.
The reason people consider RISC-V to be groundbreaking isn't really due to specifics of its design: The thing that really sets the RISC-V ISA apart from its predecessors is that it's a free and open standard, which means the ISA is publicly available. There is no license fee for using the ISA. The standard does not define any microarchitecture or business model, leaving what you do with the ISA up to you.
However, the license is permissive enough that if you make a RISC-V implementation, you aren’t required to make that implementation open-source – in fact, you could license it to make it completely proprietary. This is unlike the “copyleft” principle used in stricter open-source licenses like the GNU GPL, where the rights to use, modify, and redistribute some code are provided under the condition that the distribution terms remain unchanged – meaning that no version of something licensed under the GPL can be made proprietary.
The fact that RISC-V still allows proprietary implementations has attracted some ire and confusion – but that’s not new, since the definition of “open source” has been murky even outside of this debate. RISC-V is definitely changing the computing landscape – the startup SiFive, which designs implementations of the RISC-V ISA and licenses them to other companies, has received generous investment from Intel, which has historically focused on x86 processors. Intel is now building its own RISC-V development platform, signaling a shift in Intel’s confidence in the success of RISC-V. The question, though, is whether this kind of change is “in the spirit of open-source”. After all, to even hope of creating a processor that could compete with the duopoly of Intel and ARM in the same way that Linux challenges Windows and MacOS, you’d need a highly optimized design, not even to mention the immense costs involved in manufacturing on a similar scale to Intel and ARM.
From what I can see, RISC-V isn’t yet the Linux of ISAs. It remains to be seen whether RISC-V’s open standard will actually open up the market for consumer chips for challengers, or whether it will just benefit established companies like Intel more, due to the manufacturing capabilities on their side.